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Thursday, November 29, 2018
10:30 AM - 11:30 AM
CNLS Conference Room (TA-3, Bldg 1690)

Seminar

Scalable Performance Prediction of Codes on CPUs and GPUs

Gopinath Chennupati
Los Alamos National Laboratory, CCS-3

We live in an era where processor vendors (Intel, NVIDIA, AMD, etc) come up with a number of novel hardware architectures. At the same time, the motivation to build exascale computers in the US and around the world instigates the use of these novel processors. Before spending hundreds of millions of dollars on these future architectures, is it possible to identify and/or evaluate the most promising configurations for our particular applications? At LANL, we are developing a scalable performance prediction capability (Performance Prediction Toolkit (PPT)) that helps to draw useful insights about the current and future architectures. PPT is a parameterized runtime prediction framework that contains a suite of hardware and application models. On CPUs, we offer analytical models that rely on fine grained control flow graphs, cache hierarchies, basic block analysis and their probabilities of execution. We also show that how easy it is to simulate a 16+ million node super computer using a few physical nodes in one of the existing in-house HPC clusters.

Host: Kari Sentz